The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundancy circuit.
The redundancy circuit has been used in a semiconductor memory device such as a dynamic random access memory device and a static random access memory device for remedy of defective devices for improvement in yield of the devices. The redundancy circuit is incorporated with a large number of fuses for redundancy remedy programming. Those fuses are provided on a predetermined region where a window is formed so that a laser beam is irradiated through a window onto the fuse to cut the fuse, for which reason any interconnections are prevented from extending through the window region. It is impossible that the fuses are formed under the interconnection layers for reduction in area of the chip. This provides a limitation to reduce the chip size.
In recent years, the scaling up of the memory cells have been improved due to development in scaling down of the transistors and interconnections to be integrated, whereby the redundancy circuit scale is also increased. As compared to the development in design techniques of the transistors and interconnections, the development speed of the fuse pitch design rule is slower, whereby the occupied area of the redundancy circuit is increased. This is one of the serious problem in realizing a possible chip size shrinkage.
FIG. 1 is a plan view illustrative of a conventional layout of a semiconductor memory device having cell plates and fuses. The semiconductor memory device 21 has four plates, bonding pads 24, 25 and sets of fuses 23 provided between adjacent two cell plates 22. The region where the fuses 23 are provided have windows. The programming of the redundancy circuit is carried out by irradiation of the laser through the window onto the fuses. This window region has no interconnections. Namely, any interconnections are required to extend to avoid this window regions having the fuses 23. This provides the limitation of the freedom in design of the layout of the interconnections.
In the above circumstances, it has been required to develop a novel layout of fuses in the redundancy circuits for enabling the chip size to be reduced.